using System;

namespace RapidHDL
{
	/// <summary>
	/// Summary description for Not.
	/// </summary>
	public class Not : TruthTableComponent
	{
		public NodeVector InputNodes;
		public NodeVector OutputNodes;

		public Not(Component poParentComponent, string psName) : base (poParentComponent,psName)
		{
			this.GetTruthTable("Not",1,1);
			InputNodes = this.CreateNodeVector("In",1,NodeFlowType.Sink);
			OutputNodes = this.CreateNodeVector("Out",1,NodeFlowType.Source);
		}

		protected override void GenerateTruthTable()
		{
			this.TruthTable.AddTableEntry("1","0");
			this.TruthTable.AddTableEntry("0","1");
		}

		public override bool TransformStructureToVerilog()
		{
			WriteVerilogLookupTable();
			return true;
		}

		protected override Component TestBuildStructure(Component poTopComponent, string psTestName)
		{
			return new Not(poTopComponent,"testNot");
		}

		protected override string TestComponent(Clock poClock, Component poTestComponent, string psTestName)
		{
			string sTestId;
			Not oNot = (Not)poTestComponent;

			sTestId = "0 = 1";
			oNot.InputNodes[0].NodeState = (NodeState)0;
			poClock.DoClock(1.0);
			if(oNot.OutputNodes[0].NodeState != (NodeState)1)
				return sTestId;

			sTestId = "1 = 0";
			oNot.InputNodes[0].NodeState = (NodeState)1;
			poClock.DoClock(1.0);
			if(oNot.OutputNodes[0].NodeState != (NodeState)0)
				return sTestId;

			sTestId = "x = x";
			oNot.InputNodes[0].NodeState = NodeState.Undefined;
			poClock.DoClock(1.0);
			if(oNot.OutputNodes[0].NodeState != NodeState.Undefined)
				return sTestId;

			return "";
		}
	}
}
